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[RISCV] Codegen support for atomic operations on RV32I

Authored by asb on Jun 13 2018, 4:58 AM.

Description

[RISCV] Codegen support for atomic operations on RV32I

This patch adds lowering for atomic fences and relies on AtomicExpandPass to
lower atomic loads/stores, atomic rmw, and cmpxchg to __atomic_* libcalls.

test/CodeGen/RISCV/atomic-* are modelled on the exhaustive
test/CodeGen/PPC/atomics-regression.ll, and will prove more useful once RV32A
codegen support is introduced.

Fence mappings are taken from table A.6 in the current draft of version 2.3 of
the RISC-V Instruction Set Manual, which incorporates the memory model changes
and definitions contributed by the RISC-V Memory Consistency Model task group.

Differential Revision: https://reviews.llvm.org/D47587

llvm-svn: 334590

Details

Committed
asbJun 13 2018, 4:58 AM
Differential Revision
D47587: [RISCV] Codegen support for atomic operations on RV32I
Parents
rG0f8df3e35ab3: Revert "[clangd] Log completion context type. NFC"
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