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[AArch64] optimise v4f16 fcmps to utilise vector instructions

Authored by carwil on Jan 22 2018, 6:16 AM.

Description

[AArch64] optimise v4f16 fcmps to utilise vector instructions

Improves the code generation for v4f16 FCMP instructions when FullFP16 is not supported.
Generating FCTVL(s) rather than a longer series of FCVTs.

Differential Revision: https://reviews.llvm.org/D41772

llvm-svn: 323118

Details

Committed
carwilJan 22 2018, 6:16 AM
Differential Revision
D41772: [AArch64] optimise v4f16 FCMPs to utilise vector instructions
Parents
rG28d8a49f4276: [ThinLTO] Re-commit of dot dumper after test fix
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