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[X86] Raise the latency for VectorImul from 4 to 5 in Skylake scheduler models

Authored by craig.topper on Feb 11 2020, 11:04 AM.

Description

[X86] Raise the latency for VectorImul from 4 to 5 in Skylake scheduler models

Based on uops.info these should have 5 cycle latency as they did on Haswell/Broadwell. I have no additional internal information from Intel.

This was also shown as a discrepancy in the spreadsheet that was sent with an early llvm-dev post about llvm-exegesis.
It also matches Agner Fog.

Differential Revision: https://reviews.llvm.org/D74357

Details

Committed
craig.topperFeb 11 2020, 11:24 AM
Differential Revision
D74357: [X86] Raise the latency for VectorImul from 4 to 5 in Skylake scheduler models
Parents
rG9220bbc9091d: [gn build] Port 453a8f3af78
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