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[MCA] [In-order pipeline] Fix for 0 latency instruction causing assertion to…

Authored by holland11 on Jun 20 2021, 7:12 PM.

Description

[MCA] [In-order pipeline] Fix for 0 latency instruction causing assertion to fail.

0 latency instructions now get processed and retired properly within the in-order pipeline. Had to fix a bug within TimelineView.cpp as well that would show up when a 0 latency instruction was the first instruction in the source.

Differential Revision: https://reviews.llvm.org/D104675