[AggressiveInstCombine] Add logical shift right instr to `TruncInstCombine` DAG

Authored by anton-afanasyev on Aug 17 2021, 3:49 AM.


[AggressiveInstCombine] Add logical shift right instr to TruncInstCombine DAG

Add lshr instruction to the DAG post-dominated by trunc, allowing
TruncInstCombine to reduce bitwidth of expressions containing
these instructions.

We should be shifting by less than the target bitwidth.
Also it is sufficient to require that all truncated bits
of the value-to-be-shifted are zeros: https://alive2.llvm.org/ce/z/_LytbB

Alive2 variable-length proof:
https://godbolt.org/z/1srE1aqzf => s/32/8/ => https://alive2.llvm.org/ce/z/StwPia

Part of https://reviews.llvm.org/D107766

Differential Revision: https://reviews.llvm.org/D108201