[AggressiveInstCombine] Add logical shift right instr to TruncInstCombine DAG
Add lshr instruction to the DAG post-dominated by trunc, allowing
TruncInstCombine to reduce bitwidth of expressions containing
We should be shifting by less than the target bitwidth.
Also it is sufficient to require that all truncated bits
of the value-to-be-shifted are zeros: https://alive2.llvm.org/ce/z/_LytbB
Part of https://reviews.llvm.org/D107766
Differential Revision: https://reviews.llvm.org/D108201