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[ARM] Introduce MVEEXT ISel lowering

Authored by dmgreen on Jul 12 2021, 11:21 PM.

Description

[ARM] Introduce MVEEXT ISel lowering

Similar to D91921 (and D104515) this introduces two MVESEXT and MVEZEXT
nodes that larger-than-legal sext and zext are lowered to. These either
get optimized away or end up becoming a series of stack loads/store, in
order to perform the extending whilst keeping the order of the lanes
correct. They are generated from v8i16->v8i32, v16i8->v16i16 and
v16i8->v16i32 extends, potentially with a intermediate extend for the
larger v16i8->v16i32 extend. A number of combines have been added for
obvious cases that come up in tests, notably MVEEXT of shuffles. More
may be needed in the future, but this seems to cover most of the cases
that come up in the tests.

Differential Revision: https://reviews.llvm.org/D105090

Details

Committed
dmgreenJul 12 2021, 11:21 PM
Differential Revision
D105090: [ARM] Introduce MVEEXT ISel lowering
Parents
rGd7d9c577ed33: [NFC] Edit the comment in M68kInstrInfo::ExpandMOVSZX_RM
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