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[ARM] MVE predicate register support

Authored by dmgreen on Jul 24 2019, 4:51 AM.

Description

[ARM] MVE predicate register support

This adds support code for building and shuffling i1 predicate registers. It
generally uses two basic principles, either converting the predicate into an
scalar (through a PREDICATE_CAST) and doing scalar operations on it there, or
by converting the register to an full vector register and back.

Some of the code here is a not super efficient but will hopefully cover most
cases of moving i1 vectors around and can be improved in subsequent patches.

Some code by David Sherwood.

Differential Revision: https://reviews.llvm.org/D65052

llvm-svn: 366890

Details

Committed
dmgreenJul 24 2019, 4:51 AM
Differential Revision
D65052: [ARM] MVE predicate register support
Parents
rGb09bc8a27dd7: Revert "Revert "[lldb] [Process/NetBSD] Fix constructor after r363707""
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