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[RISCV] Transform unaligned RVV vector loads/stores to aligned ones

Authored by frasercrmck on Jun 9 2021, 7:17 AM.

Description

[RISCV] Transform unaligned RVV vector loads/stores to aligned ones

This patch adds support for loading and storing unaligned vectors via an
equivalently-sized i8 vector type, which has support in the RVV
specification for byte-aligned access.

This offers a more optimal path for handling of unaligned fixed-length
vector accesses, which are currently scalarized. It also prevents
crashing when LegalizeDAG sees an unaligned scalable-vector load/store
operation.

Future work could be to investigate loading/storing via the largest
vector element type for the given alignment, in case that would be more
optimal on hardware. For instance, a 4-byte-aligned nxv2i64 vector load
could loaded as nxv4i32 instead of as nxv16i8.

Reviewed By: craig.topper

Differential Revision: https://reviews.llvm.org/D104032

Details

Committed
frasercrmckJun 14 2021, 10:12 AM
Reviewer
craig.topper
Differential Revision
D104032: [RISCV] Transform unaligned RVV vector loads/stores to aligned ones
Parents
rGc58cf692f419: [flang] Move buffer runtime test to GTest
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