[TableGen] Allow DAG isel patterns to override default operands.

Authored by simon_tatham on Jul 4 2019, 1:43 AM.


[TableGen] Allow DAG isel patterns to override default operands.

When a Tablegen instruction description uses OperandWithDefaultOps,
isel patterns for that instruction don't have to fill in the default
value for the operand in question. But the flip side is that they
actually can't override the defaults even if they want to.

This will be very inconvenient for the Arm backend, when we start
wanting to write isel patterns that generate the many MVE predicated
vector instructions, in the form with predication actually enabled. So
this small Tablegen fix makes it possible to write an isel pattern
either with or without values for a defaulted operand, and have the
default values filled in only if they are not overridden.

If all the defaulted operands come at the end of the instruction's
operand list, there's a natural way to match them up to the arguments
supplied in the pattern: consume pattern arguments until you run out,
then fill in any missing instruction operands with their default
values. But if defaulted and non-defaulted operands are interleaved,
it's less clear what to do. This does happen in existing targets (the
first example I came across was KILLGT, in the AMDGPU/R600 backend),
and of course they expect the previous behaviour (that the default for
those operands is used and a pattern argument is not consumed), so for
backwards compatibility I've stuck with that.

Reviewers: nhaehnle, hfinkel, dmgreen

Subscribers: mehdi_amini, javed.absar, tpr, kristof.beyls, steven_wu, dexonsmith, llvm-commits

Tags: #llvm

Differential Revision: https://reviews.llvm.org/D63814

llvm-svn: 365114


simon_tathamJul 4 2019, 1:43 AM
Differential Revision
D63814: [TableGen] Allow DAG isel patterns to override default operands.
rGd2a9ec29d0f8: [ARM] MVE bitwise instruction patterns