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[RISCV] Add new vector instructions in v0.10.
c7189ba78578
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Authored by HsiangKai on Feb 1 2021, 12:08 AM.

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Description

[RISCV] Add new vector instructions in v0.10.

Add new vector instructions in v0.10.
- load/store for mask value vle1.v vse1.v
- vsetivli for 0-31 immediate vector length.
Rename vector instructions in v0.10.
- vfrsqrte7 -> vfrsqrt7
- vfrece7 -> vfrec7
Reserve memory width encodings for EEW>128b.

Differential Revision: https://reviews.llvm.org/D95781

Details

Committed

Feb 2 2021, 9:28 PM

Differential Revision

D95781: [RISCV] Add new vector instructions in v0.10.

Parents

rG98b71c53517f: [Docs] Update HowToSubmitABug

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Event Timeline

HsiangKai committed rGc7189ba78578: [RISCV] Add new vector instructions in v0.10. (authored by HsiangKai).Feb 2 2021, 9:28 PM

HsiangKai added an edge: D95781: [RISCV] Add new vector instructions in v0.10..

Changes (28)

Path

Size

llvm/

include/

llvm/

IR/

IntrinsicsRISCV.td

lib/

Target/

RISCV/

RISCVCleanupVSETVLI.cpp

RISCVExpandPseudoInsts.cpp

RISCVISelDAGToDAG.cpp

RISCVInstrFormatsV.td

RISCVInstrInfoV.td

RISCVInstrInfoVPseudos.td

test/

CodeGen/

RISCV/

rvv/

cleanup-vsetivli.mir

rv32-vsetvli-intrinsics.ll

rv64-vsetvli-intrinsics.ll

vfrsqrt7-rv32.ll

vfrsqrt7-rv64.ll

vfrece7-rv32.ll

vfrece7-rv64.ll

vfrsqrte7-rv32.ll

vfrsqrte7-rv64.ll

MC/

RISCV/

rvv/

rGc7189ba78578

llvm/include/llvm/IR/IntrinsicsRISCV.td

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llvm/lib/Target/RISCV/RISCVCleanupVSETVLI.cpp

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llvm/lib/Target/RISCV/RISCVExpandPseudoInsts.cpp

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llvm/lib/Target/RISCV/RISCVISelDAGToDAG.cpp

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llvm/lib/Target/RISCV/RISCVInstrFormatsV.td

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llvm/lib/Target/RISCV/RISCVInstrInfoV.td

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llvm/lib/Target/RISCV/RISCVInstrInfoVPseudos.td

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llvm/test/CodeGen/RISCV/rvv/cleanup-vsetivli.mir

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llvm/test/CodeGen/RISCV/rvv/rv32-vsetvli-intrinsics.ll

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llvm/test/CodeGen/RISCV/rvv/rv64-vsetvli-intrinsics.ll

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llvm/test/CodeGen/RISCV/rvv/vfrec7-rv32.ll

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llvm/test/CodeGen/RISCV/rvv/vfrec7-rv64.ll

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llvm/test/CodeGen/RISCV/rvv/vfrsqrt7-rv32.ll

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llvm/test/CodeGen/RISCV/rvv/vfrsqrt7-rv64.ll

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llvm/test/CodeGen/RISCV/rvv/vle1-rv32.ll

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llvm/test/CodeGen/RISCV/rvv/vle1-rv64.ll

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llvm/test/CodeGen/RISCV/rvv/vse1-rv32.ll

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llvm/test/CodeGen/RISCV/rvv/vse1-rv64.ll

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llvm/test/CodeGen/RISCV/vfrece7-rv32.ll

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llvm/test/CodeGen/RISCV/vfrece7-rv64.ll

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llvm/test/CodeGen/RISCV/vfrsqrte7-rv32.ll

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llvm/test/CodeGen/RISCV/vfrsqrte7-rv64.ll

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llvm/test/MC/RISCV/rvv/fothers.s

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llvm/test/MC/RISCV/rvv/invalid.s

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llvm/test/MC/RISCV/rvv/load.s

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llvm/test/MC/RISCV/rvv/store.s

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llvm/test/MC/RISCV/rvv/vsetvl.s

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llvm/test/MC/RISCV/rvv/zvlsseg.s

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