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[AArch64][SVE] Asm: Support for ADR instruction.

Authored by sdesmalen on Jul 9 2018, 2:58 AM.

Description

[AArch64][SVE] Asm: Support for ADR instruction.

Supporting various addressing modes:

  • adr z0.s, [z0.s, z0.s]
  • adr z0.s, [z0.s, z0.s, lsl #<shift>]
  • adr z0.d, [z0.d, z0.d]
  • adr z0.d, [z0.d, z0.d, lsl #<shift>]
  • adr z0.d, [z0.d, z0.d, uxtw #<shift>]
  • adr z0.d, [z0.d, z0.d, sxtw #<shift>]

Reviewers: rengolin, fhahn, SjoerdMeijer, samparker, javed.absar

Reviewed By: SjoerdMeijer

Differential Revision: https://reviews.llvm.org/D48870

llvm-svn: 336533

Details

Committed
sdesmalenJul 9 2018, 2:58 AM
Reviewer
SjoerdMeijer
Differential Revision
D48870: [AArch64][SVE] Asm: Support for ADR instruction.
Parents
rG16958bb63603: Try to fix build bot after r336524
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