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[AMDGPU] Correct rmw atomics s_waitcnt generation

Authored by t-tye on Feb 15 2021, 7:22 PM.

Description

[AMDGPU] Correct rmw atomics s_waitcnt generation

The AMD GPU SIMemoryLegalizer was using the ordering address space
rather than the instruction address space when determining the
s_waitcnt to generate to ensure that a read-modify-write atomic has
completed. This resulted in additional unnecessary counters being
waited on.

Differential Revision: https://reviews.llvm.org/D96743

Details

Committed
t-tyeFeb 16 2021, 5:32 PM
Differential Revision
D96743: [AMDGPU] Correct rmw atomics s_waitcnt generation
Parents
rGf456959a9331: [gn build] Port 6fd5ccff72ee
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