HomePhabricator

[X86] Fix tile register spill issue.

Authored by LuoYuanke on Dec 30 2020, 9:47 PM.

Description

[X86] Fix tile register spill issue.

The tile register spill need 2 instructions.
%46:gr64_nosp = MOV64ri 64
TILESTORED %stack.2, 1, killed %46:gr64_nosp, 0, $noreg, %43:tile
The first instruction load the stride to a GPR, and the second
instruction store tile register to stack slot. The optimization of merge
spill instruction is done after register allocation. And spill tile
register need create a new virtual register to for stride, so we can't
hoist tile spill instruction in postOptimization() of register
allocation. We can't hoist TILESTORED alone and we can't hoist the 2
instuctions together because MOV64ri will clobber some GPR. This patch
is to disble the spill merge for any spill which need 2 instructions.

Differential Revision: https://reviews.llvm.org/D93898

Details

Committed
LuoYuankeJan 11 2021, 2:35 AM
Differential Revision
D93898: [X86] Fix tile register spill issue.
Parents
rG1677c86124e5: [clangd] Add metrics for go-to-implementation.
Branches
Unknown
Tags
Unknown