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[RISCV] Add new SchedRead SchedWrite

Authored by shiva0217 on Feb 23 2020, 10:21 PM.

Description

[RISCV] Add new SchedRead SchedWrite

The patch fixes some typos and introduces ReadFMemBase, ReadFSGNJ32,
ReadFSGNJ64, WriteFSGNJ32, WriteFSGNJ64, ReadFMinMax32, ReadFMinMax64,
WriteFMinMax32, WriteFMinMax64, so the target CPU with different pipeline model
could use them to describe latency.

Differential Revision: https://reviews.llvm.org/D75515

Details

Committed
shiva0217Mar 9 2020, 9:12 AM
Differential Revision
D75515: [RISCV] Add new SchedRead and SchedWrite
Parents
rGdaf686b7b93e: [AMDGPU] Remove unused SchedWrite class
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