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[CodeGen] Prepare for introduction of v3 and v5 MVTs

Authored by tpr on Mar 17 2019, 2:43 PM.

Description

[CodeGen] Prepare for introduction of v3 and v5 MVTs

AMDGPU would like to have MVTs for v3i32, v3f32, v5i32, v5f32. This
commit does not add them, but makes preparatory changes:

  • Exclude non-legal non-power-of-2 vector types from ComputeRegisterProp mechanism in TargetLoweringBase::getTypeConversion.
  • Cope with SETCC and VSELECT for odd-width i1 vector when the other vectors are legal type.

Some of this patch is from Matt Arsenault, also of AMD.

Differential Revision: https://reviews.llvm.org/D58899

Change-Id: Ib5f23377dbef511be3a936211a0b9f94e46331f8
llvm-svn: 356350

Details

Committed
tprMar 17 2019, 2:43 PM
Differential Revision
D58899: [CodeGen] Prepare for introduction of v3 and v5 MVTs
Parents
rGbaa94ef03bcc: [ARM] Check that CPSR does not have other uses
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