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[AVR] Fix expansion of NEGW

Authored by aykevl on Feb 20 2021, 4:23 PM.

Description

[AVR] Fix expansion of NEGW

The previous expansion used SBCI, which is incorrect because the NEGW
pseudo instruction accepts a DREGS operand (2xGPR8) and SBCI only allows
LD8 registers. One solution could be to correct the NEGW pseudo
instruction, but another solution is to use a different instruction
(sbc) that does accept a GPR8 register and therefore allows more freedom
to the register allocator.

The output now matches avr-gcc for the following code:

int foo(int n) {
    return -n;
}

I've found this issue using the machine instruction verifier: it was
complaining about the wrong register class in NEGWRd.mir.

Differential Revision: https://reviews.llvm.org/D97131

Details

Committed
aykevlMar 3 2021, 6:36 AM
Differential Revision
D97131: [AVR] Fix expansion of NEGW
Parents
rG4f6d7985d47a: [AVR] Add register aliases XL, YH, etc
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