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[RISCV] Prevent assertion in the assembler if vmerge or vfmerge are given a V0…
b094eaa39232
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Authored by craig.topper on Dec 14 2020, 5:19 PM.

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Description

[RISCV] Prevent assertion in the assembler if vmerge or vfmerge are given a V0 destination.

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Committed

Dec 14 2020, 5:22 PM

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rG2cf12ae0cc3f: [RISCV] Handle Match_InvalidSImm5 in RISCVAsmParser::MatchAndEmitInstruction

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Event Timeline

craig.topper committed rGb094eaa39232: [RISCV] Prevent assertion in the assembler if vmerge or vfmerge are given a V0… (authored by craig.topper).Dec 14 2020, 5:22 PM

Herald added subscribers: arcbbb, HsiangKai. · View Herald TranscriptDec 14 2020, 5:28 PM

Changes (2)

Path

Size

llvm/

lib/

Target/

RISCV/

AsmParser/

RISCVAsmParser.cpp

test/

MC/

RISCV/

rvv/

rGb094eaa39232

llvm/lib/Target/RISCV/AsmParser/RISCVAsmParser.cpp

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llvm/test/MC/RISCV/rvv/invalid.s

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