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[RISCV] Teach RISCVInsertVSETVLI::needVSETVLI to handle mask register…

Authored by craig.topper on Oct 28 2021, 3:09 PM.

Description

[RISCV] Teach RISCVInsertVSETVLI::needVSETVLI to handle mask register instructions better.

If the VL operand of a mask register instruction comes from an
explicit vsetvli with a different VTYPE, we can still avoid needing
a vsetvli as long as the SEW/LMUL ratio is the same and policy bits
match.

Differential Revision: https://reviews.llvm.org/D112762