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[RISCV] Add support for -ffixed-xX flags

Authored by simoncook on Oct 22 2019, 1:25 PM.

Description

[RISCV] Add support for -ffixed-xX flags

This adds support for reserving GPRs such that the compiler will not
choose a register for register allocation. The implementation follows
the same design as for AArch64; each reserved register becomes a target
feature and used for getting the reserved registers for a given
MachineFunction. The backend checks that it does not need to write to
any reserved register; if it does a relevant error is generated.

Differential Revision: https://reviews.llvm.org/D67185

Details

Committed
simoncookOct 22 2019, 1:25 PM
Differential Revision
D67185: [RISCV] Add support for -ffixed-xX flags
Parents
rG68f5ca4e19c1: [HIP] Add option -fgpu-allow-device-init
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