[RISCV] Rename FPRs and use Register arithmetic

Authored by luismarques on Sep 27 2019, 8:49 AM.


[RISCV] Rename FPRs and use Register arithmetic

The new names for FPRs ensure that the Register values within the same class are
enumerated consecutively (the order is determined by the LessRecordRegister
function object). Where there were tables mapping between 32- and 64-bit FPRs
(and vice versa) this patch replaces them with Register arithmetic. The
enumeration order between different register classes is expected to continue to
be arbitrary, although it does impact the conversion from the (overloaded) asm
FPR names to Register values, and therefore might require updates to the target
if the sorting algorithm is changed. Static asserts were added to ensure that
changes to the ordering that would impact the current implementation are

Differential Revision: https://reviews.llvm.org/D67423

llvm-svn: 373096