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[MVT] Add new MVT types for RISC-V vector.

Authored by HsiangKai on Fri, Jun 12, 2:02 AM.

Description

[MVT] Add new MVT types for RISC-V vector.

In RISC-V vector extension, users could group multiple vector registers
as one pseudo register. In mixed width operations, users could use
partial vector registers to reduce the register pressure. The parameter
to control register grouping and partial use is called LMUL. LMUL is a
part of the type. So, we have a bunch of vector types. In order to
support all these types, we need new MVT types in LLVM. In this patch, I
added several MVT types that are used in RISC-V vector implementation.
This is a standalone patch for MVT types without RISC-V related implementation.

Differential revision: https://reviews.llvm.org/D81724

Details

Committed
HsiangKaiTue, Jun 30, 10:07 AM
Differential Revision
D81724: [MVT] Add new MVT types for RISC-V vector.
Parents
rG787b1a474687: [InstCombine] New FMA tests and regenerate tests. NFC
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