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[AArch64] Combine vector shift instructions in SelectionDAG

Authored by asavonic on May 18 2021, 5:54 AM.

Description

[AArch64] Combine vector shift instructions in SelectionDAG

bswap.v2i16 + sitofp in LLVM IR generate a sequence of:

  • REV32 + USHR for bswap.v2i16
  • SHL + SSHR + SCVTF for sext to v2i32 and scvt

The shift instructions are excessive as noted in PR24820, and they can
be optimized to just SSHR.

Differential Revision: https://reviews.llvm.org/D102333

Details

Committed
asavonicMay 20 2021, 12:50 AM
Differential Revision
D102333: [AArch64] Combine shift instructions in SelectionDAG
Parents
rG99a198641cbb: [mlir][Python][linalg] Fix to limit size of SmallVector.
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