[ARM] Code-generation infrastructure for MVE.

Authored by simon_tatham on Jun 25 2019, 9:48 AM.


[ARM] Code-generation infrastructure for MVE.

This provides the low-level support to start using MVE vector types in
LLVM IR, loading and storing them, passing them to asm statements
containing hand-written MVE vector instructions, and *if* you have the
hard-float ABI turned on, using them as function parameters.

(In the soft-float ABI, vector types are passed in integer registers,
and combining all those 32-bit integers into a q-reg requires support
for selection DAG nodes like insert_vector_elt and build_vector which
aren't implemented yet for MVE. In fact I've also had to add
arm_aapcs_vfpcc to a couple of existing tests to avoid that

Specifically, this commit adds support for:

  • spills, reloads and register moves for MVE vector registers
  • ditto for the VPT predication mask that lives in VPR.P0
  • make all the MVE vector types legal in ISel, and provide selection DAG patterns for BITCAST, LOAD and STORE
  • make loads and stores of scalar FP types conditional on hasFPRegs() rather than hasVFP2Base(). As a result a few existing tests needed their llc command lines updating to use -mattr=-fpregs as their method of turning off all hardware FP support.

Reviewers: dmgreen, samparker, SjoerdMeijer

Subscribers: javed.absar, kristof.beyls, hiraditya, llvm-commits

Tags: #llvm

Differential Revision: https://reviews.llvm.org/D60708

llvm-svn: 364329


simon_tathamJun 25 2019, 9:48 AM
Differential Revision
D60708: [ARM] Code-generation infrastructure for MVE.
rGd0f96be2c781: [FPEnv] A missing crucial step was undocumented.