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[ARC] Add more load/store variants.

Authored by petecoup on Mar 14 2019, 1:50 PM.

Description

[ARC] Add more load/store variants.

On ARC ISA, general format of load instruction is this:

LD<zz><.x><.aa><.di> a, [b,c]

And general format of store is this:

ST<zz><.aa><.di> c, [b,s9]

Where:

<zz> is data size field and can be one of

<empty> (bits 00) - Word (32-bit), default behavior
B             (bits 01) - Byte
H             (bits 10) - Half-word (16-bit)

<.x> is data extend mode:

<empty> (bit 0) - If size is not Word(32-bit), then data is zero extended
X       (bit 1) - If size is not Word(32-bit), then data is sign extended

<.aa> is address write-back mode:

<empty> (bits 00) - no write-back
.AW  (bits 01) - Preincrement, base register updated pre memory transaction
.AB  (bits 10) - Postincrement, base register updated post memory transaction

<.di> is cache bypass mode:

<empty> (bit 0) - Cached memory access, default mode
.DI     (bit 1) - Non-cached data memory access

This patch adds these load/store instruction variants to the ARC backend.

Patch By Denis Antrushin! <denis@synopsys.com>

Differential Revision: https://reviews.llvm.org/D58980

llvm-svn: 356200