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[tblgen][disasm] Allow multiple encodings to disassemble to the same instruction

Authored by dsanders on Jun 18 2019, 2:56 PM.

Description

[tblgen][disasm] Allow multiple encodings to disassemble to the same instruction

Summary:
Add an AdditionalEncoding class which can be used to define additional encodings
for a given instruction. This causes the disassembler to add an additional
encoding to its matching tables that map to the specified instruction.

Usage:

def ADD1 : Instruction {
  bits<8> Reg;
  bits<32> Inst;

  let Size = 4;
  let Inst{0-7} = Reg;
  let Inst{8-14} = 0;
  let Inst{15} = 1; // Continuation bit
  let Inst{16-31} = 0;
  ...
}
def : AdditionalEncoding<ADD1> {
  bits<8> Reg;
  bits<16> Inst; // You can also have bits<32> and it will still be a 16-bit encoding
  let Size = 2;
  let Inst{0-3} = 0;
  let Inst{4-7} = Reg;
  let Inst{8-15} = 0;
  ...
}

with those definitions, llvm-mc will successfully disassemble both of these:

0x01 0x00
0x10 0x80 0x00 0x00

to:

ADD1 r1

Depends on D52366

Reviewers: bogner, charukcs

Reviewed By: bogner

Subscribers: nlguillemot, nhaehnle, llvm-commits

Tags: #llvm

Differential Revision: https://reviews.llvm.org/D52369

llvm-svn: 363744