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[AArch64][SME] Add load and store instructions

Authored by c-rhodes on Jul 16 2021, 2:14 AM.

Description

[AArch64][SME] Add load and store instructions

This patch adds support for following contiguous load and store
instructions:

  • LD1B, LD1H, LD1W, LD1D, LD1Q
  • ST1B, ST1H, ST1W, ST1D, ST1Q

A new register class and operand is added for the 32-bit vector select
register W12-W15. The differences in the following tests which have been
re-generated are caused by the introduction of this register class:

  • llvm/test/CodeGen/AArch64/GlobalISel/irtranslator-inline-asm.ll
  • llvm/test/CodeGen/AArch64/GlobalISel/regbank-inlineasm.mir
  • llvm/test/CodeGen/AArch64/stp-opt-with-renaming-reserved-regs.mir
  • llvm/test/CodeGen/AArch64/stp-opt-with-renaming.mir

D88663 attempts to resolve the issue with the store pair test
differences in the AArch64 load/store optimizer.

The GlobalISel differences are caused by changes in the enum values of
register classes, tests have been updated with the new values.

The reference can be found here:
https://developer.arm.com/documentation/ddi0602/2021-06

Reviewed By: CarolineConcatto

Differential Revision: https://reviews.llvm.org/D105572

Details

Committed
c-rhodesJul 16 2021, 3:11 AM
Reviewer
CarolineConcatto
Differential Revision
D105572: [AArch64][SME] Add load and store instructions
Parents
rGd046fb62b7e7: [lldb][AArch64] Refactor memory tag range handling
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