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[RISCV] Update RVV shift intrinsic tests to use XLEN bit as shift amount.

Authored by khchen on Mar 11 2021, 8:01 AM.

Description

[RISCV] Update RVV shift intrinsic tests to use XLEN bit as shift amount.

Fix the unexpected of using op1's element type as shift amount type.

Reviewed By: frasercrmck

Differential Revision: https://reviews.llvm.org/D98501

Details

Committed
khchenMar 17 2021, 10:47 AM
Reviewer
frasercrmck
Differential Revision
D98501: [RISCV] Update RVV shift intrinsic tests to use XLEN bit as shift amount.
Parents
rGe2935dcfc4c4: [TTI] Add a Mask to getShuffleCost
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