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[RISCV] Add codegen support for atomic load/stores with RV32A

Authored by asb on Jun 13 2018, 5:04 AM.

Description

[RISCV] Add codegen support for atomic load/stores with RV32A

Fences are inserted according to table A.6 in the current draft of version 2.3
of the RISC-V Instruction Set Manual, which incorporates the memory model
changes and definitions contributed by the RISC-V Memory Consistency Model
task group.

Instruction selection failures will now occur for 8/16/32-bit atomicrmw and
cmpxchg operations when targeting RV32IA until lowering for these operations
is added in a follow-on patch.

Differential Revision: https://reviews.llvm.org/D47589

llvm-svn: 334591

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