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[AArch64][SVE] Add intrinsics for non-temporal gather-loads/scatter-stores

Authored by andwar on Feb 19 2020, 4:25 AM.

Description

[AArch64][SVE] Add intrinsics for non-temporal gather-loads/scatter-stores

Summary:
This patch adds the following LLVM IR intrinsics for SVE:

  1. non-temporal gather loads
    • @llvm.aarch64.sve.ldnt1.gather
    • @llvm.aarch64.sve.ldnt1.gather.uxtw
    • @llvm.aarch64.sve.ldnt1.gather.scalar.offset
  2. non-temporal scatter stores
    • @llvm.aarch64.sve.stnt1.scatter
    • @llvm.aarch64.sve.ldnt1.gather.uxtw
    • @llvm.aarch64.sve.ldnt1.gather.scalar.offset

These intrinsic are mapped to the corresponding SVE instructions
(example for half-words, zero-extending):

  • ldnt1h { z0.s }, p0/z, [z0.s, x0]
  • stnt1h { z0.s }, p0/z, [z0.s, x0]

Note that for non-temporal gathers/scatters, the SVE spec defines only
one instruction type: "vector + scalar". For this reason, we swap the
arguments when processing intrinsics that implement the "scalar +
vector" addressing mode:

  • @llvm.aarch64.sve.ldnt1.gather
  • @llvm.aarch64.sve.ldnt1.gather.uxtw
  • @llvm.aarch64.sve.stnt1.scatter
  • @llvm.aarch64.sve.ldnt1.gather.uxtw

In other words, all intrinsics for gather-loads and scatter-stores
implemented in this patch are mapped to the same load and store
instruction, respectively.

The sve2_mem_gldnt_vs multiclass (and it's counterpart for scatter
stores) from SVEInstrFormats.td was split into:

  • sve2_mem_gldnt_vec_vs_32_ptrs (32bit wide base addresses)
  • sve2_mem_gldnt_vec_vs_62_ptrs (64bit wide base addresses)

This is consistent with what we did for
@llvm.aarch64.sve.ld1.scalar.offset and highlights the actual split in
the spec and the implementation.

Reviewed by: sdesmalen

Differential Revision: https://reviews.llvm.org/D74858