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[SystemZ] Model floating-point control register

Authored by uweigand on May 13 2019, 2:47 AM.

Description

[SystemZ] Model floating-point control register

This adds the FPC (floating-point control register) as a reserved
physical register and models its use by SystemZ instructions.

Note that only the current rounding modes and the IEEE exception
masks are modeled. *Changes* of the FPC due to exceptions (in
particular the IEEE exception flags and the DXC) are not modeled.

At this point, this patch is mostly NFC, but it will prevent
scheduling of floating-point instructions across SPFC/LFPC etc.

llvm-svn: 360570

Details

Committed
uweigandMay 13 2019, 2:47 AM
Parents
rG869f934d19f7: [NativePDB] Support member function types in PdbAstBuilder
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