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[Aarch64][SVE] Add intrinsics for gather loads with 32-bits offsets

Authored by sdesmalen on Dec 3 2019, 5:52 AM.

Description

[Aarch64][SVE] Add intrinsics for gather loads with 32-bits offsets

This patch adds intrinsics for SVE gather loads for which the offsets are 32-bits wide and are:

  • unscaled
    • @llvm.aarch64.sve.ld1.gather.sxtw
    • @llvm.aarch64.sve.ld1.gather.uxtw
  • scaled (offsets become indices)
    • @llvm.arch64.sve.ld1.gather.sxtw.index
    • @llvm.arch64.sve.ld1.gather.uxtw.index

The offsets are either zero (uxtw) or sign (sxtw) extended to 64 bits.

These intrinsics map 1-1 to the corresponding SVE instructions (examples for half-words):

  • unscaled
    • ld1h { z0.s }, p0/z, [x0, z0.s, sxtw]
    • ld1h { z0.s }, p0/z, [x0, z0.s, uxtw]
  • scaled
    • ld1h { z0.s }, p0/z, [x0, z0.s, sxtw #1]
    • ld1h { z0.s }, p0/z, [x0, z0.s, uxtw #1]

Committed on behalf of Andrzej Warzynski (andwar)

Reviewers: sdesmalen, kmclaughlin, eli.friedman, rengolin, rovka, huntergr, dancgr, mgudim, efriedma

Reviewed By: sdesmalen

Tags: #llvm

Differential Revision: https://reviews.llvm.org/D70782

Details

Committed
sdesmalenDec 3 2019, 6:48 AM
Reviewer
sdesmalen
Differential Revision
D70782: [Aarch64][SVE] Add intrinsics for gather loads with 32-bits offsets
Parents
rG8dd17a13b04f: [NFCI][DebugInfo] Corrected a comment.
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