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[AArch64] Legalize horizontal fmax/fmin reductions on f16 vectors

Authored by LemonBoy on Mar 5 2021, 7:01 AM.

Description

[AArch64] Legalize horizontal fmax/fmin reductions on f16 vectors

Expand the horizontal reduction during the instruction selection phase, but only if the target doesn't support the full fp16 instruction set.

Fixes https://bugs.llvm.org/show_bug.cgi?id=49401

Reviewed By: aemerson

Differential Revision: https://reviews.llvm.org/D97840

Details

Committed
LemonBoyMar 5 2021, 7:09 AM
Reviewer
aemerson
Differential Revision
D97840: [AArch64] Legalize horizontal fmax/fmin reductions on f16 vectors
Parents
rG5fedf3074838: [mlir] Make cuInit() call thread-safe.
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