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[RISCV] Scheduler description for the Rocket core

Authored by HsiangKai on Jan 23 2020, 12:51 PM.

Description

[RISCV] Scheduler description for the Rocket core

Pipeline scheduler model for the RISC-V Rocket micro-architecture using the
MIScheduler interface. Support for both 32 and 64-bit Rocket cores is
implemented.

Differential revision: https://reviews.llvm.org/D68685

Details

Committed
evandroJan 23 2020, 5:36 PM
Differential Revision
D68685: [RISCV] Scheduler description for Rocket Core
Parents
rG90e630a95ecc: Revert "[LTO/WPD] Enable aggressive WPD under LTO option"
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