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[mlir] Fix support for lowering non-32-bit affine reductions.

Authored by ftynse on Apr 6 2021, 3:53 AM.

Description

[mlir] Fix support for lowering non-32-bit affine reductions.

The existing implementation was always creating 32-bit constants for
floating-point and integer reductions regardless of the actual type, which
resulted in invalid IR being generated for any types other than f32 and i32
when lowering affine.parallel to SCF. Use the actual type instead.

Reviewed By: chelini

Differential Revision: https://reviews.llvm.org/D99942

Details

Committed
ftynseApr 6 2021, 5:00 AM
Reviewer
chelini
Differential Revision
D99942: [mlir] Fix support for lowering non-32-bit affine reductions.
Parents
rG6fec0a34ceb0: [AMDGPU] Fix typo in regular expression checks. NFC.
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