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[RISCV] Lower inline asm constraint A for RISC-V

Authored by lewis-revill on Aug 16 2019, 3:28 AM.

Description

[RISCV] Lower inline asm constraint A for RISC-V

This allows arguments with the constraint A to be lowered to input nodes
for RISC-V, which implies a memory address stored in a register.

This patch adds the minimal amount of code required to get operands with
the right constraints to compile.

https://reviews.llvm.org/D54296

llvm-svn: 369095

Details

Committed
lewis-revillAug 16 2019, 3:28 AM
Parents
rG59894d466853: [SLPVectorizer] Silence null dereference warning. NFCI.
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