HomePhabricator

[RISCV] Scheduler description for Bullet

Authored by compilerguy on Sep 25 2020, 3:59 PM.

Description

[RISCV] Scheduler description for Bullet

Add the pipeline model for the RISC-V Bullet micro architecture.

Co-authored-by: Evandro Menezes <evandro.menezes@sifive.com>

Details

Committed
evandroSep 25 2020, 4:36 PM
Parents
rG97702c3d9234: [Object][MachO] Refine the interface of Slice
Branches
Unknown
Tags
Unknown

Event Timeline

zixuan-wu added inline comments.
/llvm/lib/Target/RISCV/RISCVSchedBullet.td
61

Hi, I have a question that why there is both BulletPipeB and BulletIDiv?
BulletPipeB is the Super of BulletIDiv, so consuming BulletIDiv is including BulletPipeB.