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[AArch64][GlobalISel] Add an optimization to select vector DUP instructions.

Authored by aemerson on Mar 19 2019, 2:43 PM.

Description

[AArch64][GlobalISel] Add an optimization to select vector DUP instructions.

This adds pattern matching for the insert+shufflevector sequence so we can
generate dup instructions instead of the current TBL sequence.

Differential Revision: https://reviews.llvm.org/D59558

llvm-svn: 356526