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[PowerPC] Avoid scalarization of vector truncate

Authored by RolandF on Feb 11 2019, 9:29 AM.

Description

[PowerPC] Avoid scalarization of vector truncate

The PowerPC code generator currently scalarizes vector truncates that would fit in a vector register, resulting in vector extracts, scalar operations, and vector merges. This patch custom lowers a vector truncate that would fit in a register to a vector shuffle instead.

Differential Revision: https://reviews.llvm.org/D56507

llvm-svn: 353724

Details

Committed
RolandFFeb 11 2019, 9:29 AM
Differential Revision
D56507: [PowerPC] Avoid scalarization of vector truncate
Parents
rGebdb021031a9: [GlobalISel][AArch64] Select G_FFLOOR
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