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[AArch64] Update MTE system register encodings

Authored by LukeCheeseman on Aug 21 2019, 2:09 AM.

Description

[AArch64] Update MTE system register encodings

The encodings for the system registers TFSRE0_EL1, TFSR_EL1 TFSR_EL2, TFSR_EL3
and TFSR_EL12 have been changed so that they consistently have CRn=5 and CRm=6
as per https://developer.arm.com/docs/ddi0487/latest.

Differential Revision: https://reviews.llvm.org/D65442

llvm-svn: 369505

Details

Committed
LukeCheesemanAug 21 2019, 2:09 AM
Differential Revision
D65442: [AArch64] Update MTE system register encodings
Parents
rG6b9d7c9da591: Removed some dead code in BugReporter and related files
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