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[InstCombine] conditional sign-extend of high-bit-extract: 'or' pattern.

Authored by lebedev.ri on Oct 20 2019, 1:52 PM.

Description

[InstCombine] conditional sign-extend of high-bit-extract: 'or' pattern.

In this pattern, all the "magic" bits that we'd add are all
high sign bits, and in the value we'd be adding to they are all unset,
not unexpectedly, so we can have an or there:
https://rise4fun.com/Alive/ups

It is possible that haveNoCommonBitsSet() should be taught about this
pattern so that we never have an add variant, but the reasoning would
need to be recursive (because of that select), so i'm not really sure
that would be worth it just yet.

llvm-svn: 375378

Details

Event Timeline

xbolva00 added inline comments.
/llvm/lib/Transforms/InstCombine/InstCombineAddSub.cpp
1106

add/or/sub