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[AMDGPU] Enable divergence driven ISel for ADD/SUB i64

Authored by alex-t on Mar 19 2020, 11:33 AM.

Description

[AMDGPU] Enable divergence driven ISel for ADD/SUB i64

Summary:
Currently we custom select add/sub with carry out to scalar form relying on later replacing them to vector form if necessary.
This change enables custom selection code to take the divergence of adde/addc SDNodes into account and select the appropriate form in one step.

Reviewers: arsenm, vpykhtin, rampitec

Reviewed By: arsenm, vpykhtin

Subscribers: kzhuravl, jvesely, wdng, nhaehnle, yaxunl, dstuttard, tpr, t-tye, hiraditya, kerbowa

Differential Revision: https://reviews.llvm.org/D76371

Details

Committed
alex-tMar 20 2020, 7:06 AM
Reviewer
arsenm
Differential Revision
D76371: [AMDGPU] Enable divergence driven ISel for ADD/SUB i64
Parents
rG6ae3eff8baac: [ARM,CDE] Implement CDE vreinterpret intrinsics
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