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[RISCV] Define vsext/vzext intrinsics.

Authored by khchen on Dec 28 2020, 8:44 AM.

Description

[RISCV] Define vsext/vzext intrinsics.

Define vsext/vzext intrinsics.and lower to V instructions.
Define new fraction register class fields in LMULInfo and a
NoReg to present invalid LMUL register classes.

Authored-by: ShihPo Hung <shihpo.hung@sifive.com>
Co-Authored-by: Zakk Chen <zakk.chen@sifive.com>

Reviewed By: craig.topper

Differential Revision: https://reviews.llvm.org/D93893

Details

Committed
khchenDec 29 2020, 4:50 PM
Reviewer
craig.topper
Differential Revision
D93893: [RISCV] Define vsext/vzext intrinsics.
Parents
rG57b8afda10b6: [gn build] Port 480936e741d
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