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Add support for (expressing) vscale.

Authored by sdesmalen on Jan 21 2020, 2:20 AM.

Description

Add support for (expressing) vscale.

In LLVM IR, vscale can be represented with an intrinsic. For some targets,
this is equivalent to the constexpr:

getelementptr <vscale x 1 x i8>, <vscale x 1 x i8>* null, i32 1

This can be used to propagate the value in CodeGenPrepare.

In ISel we add a node that can be legalized to one or more
instructions to materialize the runtime vector length.

This patch also adds SVE CodeGen support for VSCALE, which maps this
node to RDVL instructions (for scaled multiples of 16bytes) or CNT[HSD]
instructions (scaled multiples of 2, 4, or 8 bytes, respectively).

Reviewers: rengolin, cameron.mcinally, hfinkel, sebpop, SjoerdMeijer, efriedma, lattner

Reviewed by: efriedma

Tags: #llvm

Differential Revision: https://reviews.llvm.org/D68203

Details

Committed
sdesmalenJan 22 2020, 2:09 AM
Reviewer
efriedma
Differential Revision
D68203: Add support for (expressing) vscale.
Parents
rGe57a9abc4b01: [Concepts] Placeholder constraints and abbreviated templates
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