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[AMDGPU] Implemented dwordx3 variants of buffer/tbuffer load/store intrinsics

Authored by tpr on Mar 22 2019, 7:58 AM.

Description

[AMDGPU] Implemented dwordx3 variants of buffer/tbuffer load/store intrinsics

Now we have vec3 MVTs, this commit implements dwordx3 variants of the
buffer intrinsics.

On gfx6, a dwordx3 buffer load intrinsic is implemented as a dwordx4
instruction, and a dwordx3 buffer store intrinsic is not supported.
We need to support the dwordx3 load intrinsic because it is generated by
subtarget-unaware code in InstCombine.

Differential Revision: https://reviews.llvm.org/D58904

Change-Id: I016729d8557b98a52f529638ae97c340a5922a4e
llvm-svn: 356755