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[RISCV] Introduce codegen patterns for RV64M-only instructions

Authored by asb on Jan 11 2019, 11:43 PM.

Description

[RISCV] Introduce codegen patterns for RV64M-only instructions

As discussed on llvm-dev
http://lists.llvm.org/pipermail/llvm-dev/2018-December/128497.html, we have
to be careful when trying to select the *w RV64M instructions. i32 is not a
legal type for RV64 in the RISC-V backend, so operations have been promoted by
the time they reach instruction selection. Information about whether the
operation was originally a 32-bit operations has been lost, and it's easy to
write incorrect patterns.

Similarly to the variable 32-bit shifts, a DAG combine on ANY_EXTEND will
produce a SIGN_EXTEND if this is likely to result in sdiv/udiv/urem being
selected (and so save instructions to sext/zext the input operands).

Differential Revision: https://reviews.llvm.org/D53230

llvm-svn: 350993

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