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[AArch64] Improve FP16 instruction selection for vector round and vector conver…

Authored by az on Mar 6 2019, 12:30 PM.

Description

[AArch64] Improve FP16 instruction selection for vector round and vector conver from half instructions https://reviews.llvm.org/D58855

llvm-svn: 355545

Details

Committed
azMar 6 2019, 12:30 PM
Parents
rGe1012e1efb10: [X86] Add vector mulo with power of two operand tests; NFC
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