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[RISCV][MC] Fix nf encoding for vector ld/st whole register

Authored by arcbbb on Mar 8 2021, 8:15 AM.

Description

[RISCV][MC] Fix nf encoding for vector ld/st whole register

The three bit nf is one less than the number of NFIELDS,
so we manually decrement 1 for VS1/2/4/8R & VL1/2/4/8R.

Reviewed By: craig.topper

Differential revision: https://reviews.llvm.org/D98185

Details

Committed
arcbbbMar 8 2021, 7:30 PM
Reviewer
craig.topper
Differential Revision
D98185: [RISCV][MC] Fix nf encoding for vector ld/st whole register
Parents
rGf2cb3be0f926: [docs] Fix llvm-objcopy.rst
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