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[RISCV] Add inline asm constraints I, J & K for RISC-V

Authored by lewis-revill on Jun 11 2019, 5:44 AM.

Description

[RISCV] Add inline asm constraints I, J & K for RISC-V

This allows the constraints I, J & K to be used in inline asm for
RISC-V, with the following semantics (equivalent to GCC):

I: Any 12-bit signed immediate.
J: Integer zero only.
K: Any 5-bit unsigned immediate.

See the GCC definitions here:
https://gcc.gnu.org/onlinedocs/gccint/Machine-Constraints.html

Differential Revision: https://reviews.llvm.org/D54091

llvm-svn: 363055

Details