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PowerPC/SPE: Fix load/store handling for SPE

Authored by jhibbits on Jul 17 2019, 5:30 AM.

Description

PowerPC/SPE: Fix load/store handling for SPE

Summary:
Pointed out in a comment for D49754, register spilling will currently
spill SPE registers at almost any offset. However, the instructions
evstdd and evldd require a) 8-byte alignment, and b) a limit of 256
(unsigned) bytes from the base register, as the offset must fix into a
5-bit offset, which ranges from 0-31 (indexed in double-words).

The update to the register spill test is taken partially from the test
case shown in D49754.

Additionally, pointed out by Kei Thomsen, globals will currently use
evldd/evstdd, though the offset isn't known at compile time, so may
exceed the 8-bit (unsigned) offset permitted. This fixes that as well,
by forcing it to always use evlddx/evstddx when accessing globals.

Part of the patch contributed by Kei Thomsen.

Reviewers: nemanjai, hfinkel, joerg

Subscribers: kbarton, jsji, llvm-commits

Differential Revision: https://reviews.llvm.org/D54409

llvm-svn: 366318

Details

Committed
jhibbitsJul 17 2019, 5:30 AM
Differential Revision
D54409: PowerPC/SPE: Fix load/store handling for SPE
Parents
rG1e62635d0551: [MIPS GlobalISel] ClampScalar and select pointer G_ICMP
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