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The IR verifier currently supports the constrained floating point intrinsics…

Authored by kpn on Mar 27 2019, 6:30 AM.

Description

The IR verifier currently supports the constrained floating point intrinsics, but the implementation is hard to extend. It doesn't currently have an easy way to support intrinsics that, for example, lack a rounding mode. This will be needed for impending new constrained intrinsics.

This code is split out of D55897 https://reviews.llvm.org/D55897, which
itself was split out of D43515 https://reviews.llvm.org/D43515.

Reviewed by: arsenm
Differential Revision: http://reviews.llvm.org/D59830

llvm-svn: 357065

Details

Committed
kpnMar 27 2019, 6:30 AM
Reviewer
arsenm
Differential Revision
D59830: [FPEnv] Make constrained FP IR verification more flexible.
Parents
rG90d1b551e19a: [AArch64] NFC: Cleanup isAArch64FrameOffsetLegal
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